The technical data is available in the web site. It's a bit outdated. Upon signing an NDA we'll release all the needed information to start a design based on our 1st gen and 2nd gen ASICs. Multiple parties, companies and one collective already got the information.
The updated spec of our 2nd gen ASIC:
Voltage 0.63 V
Total Engines 193
Max frequency at TT corner 984 MHz
Performance 190 GHs
Power 65 W
Power/performance 0.34 W/GHs
Multiple voltages and overclocking points possible.
Does it make you more comfortable ?
Should I post working FPGA pictures ?
Verilog test bench ?
Seriously, we know what we're doing.
The ASICs will arrive on time, working. SP30 will be delivered on time and on spec.
Edit:
Some more information on the system. SP30, like the SP10 will contains two ASICs boards and one management board.
The management board will contain the same TI Sitara processor and FPGA. Beside the FPGA, it's almost identical to Beagle Bone Black.
(Unlike other vendors, we don't ship with hobby boards...)
Each ASICs board contains 15 RockerBox ASICs. The total system output is expected to be over 5.5 TH/s
We've improved our DC2DC design, and we're testing it separately on a test board.
Edit2:
We won't release any information on our 3rd gen ASIC (PickAxe) beside stating again that the design goal is to compete and win in the EH/s (Exa Hash/s) era, while eradicating (by making obsolete) a well known northern farm.
I presume that you are just a marketroid. What you just did by saying "we know what we are doing" and "verilog testbench" is to suggest that you don't have any experience with designing power-limited and noise-limited ASICs. There is obviously a small possibility that someone in your team knows it, but intentionally told you to misinform. But I somehow doubt this had happened in Israel right after shabbat.
You could make an intelligent post without disclosing any proprietary info. Bitfury for example had posted max clock speed for his chip with all hashing engines running and with just one engine running. He also posted whole slew of timing-margin and noise-margin vs. supply voltage values.
If you have no detailed BSIM (or similar analog) models of your chips at this stage then you quite clearly aren't in the "know what we are doing" category but in the "CAD monkey" category. This doesn't bode well for the successful delivery. Simon Barber of Hashfast was the most recent example on this forum: "our chip will work because Apache Redhawk says so!"
https://bitcointalk.org/index.php?topic=270384.msg2894710#msg2894710PS. In the above message all "you" should be understood as "plural you" (i.e. whole company as opposed to the person posting) with the exception of the very first.
Indeed, I'm not an ASIC technical guy.
Point taken. After Passover holiday (towards the end of next week) we'll publish some more technical data.
I do however know the exact status of the project and it's timeline. And everything I've said is true.
As explained multiple time before. The 2nd gen is a simple die shrink of our 1st gen ASIC. It's essentially the same engine.
Edit: RockerBox technical brief is here:
https://www.dropbox.com/s/c65ebuvoh5sek2f/rockerbox_brief.pdfFull datasheet will be given upon signing NDA
We'll post more technical data to "prove" project status after the Passover holiday.
This post was written by Guy Corem, Spondoolies-Tech CEO
(This user is shared between multiple Spondoolies-Tech employees)