Based on the current known specs of 28nm technology any array of chips that pumps out a combined total of 300 mhs of scrypt is going to be using right at 6000 watts at 100% efficiency, which again is never going to happen.
This is an interesting conjecture. Can you explain your reasoning in more detail ?
I, too, am really curious as to how you could back up your estimate. Are you assuming there is a minimal amount of transistors you have to use and a minimal amount of reads/writes on a on-chip memory?
Overall energy consumption is affected by many factors. Like layout of the board. for example in an ASIC, you can have memory very close to a processor significantly lowering wattage.