One SHA engine is simple, deceptively so, cram so many together on a chip and you get horrendous power and leakage issues that are more like multipipe GPUs than CPUs or SOCs or anything.
If it was sofa king straightforward, every SHA ASIC ever thought of so far would have come in below, even at power target, on time, or even at all. (AM had a fail, BFL had a fail. and don't forget they were working with reputable design and layout houses. And there might have been a couple of private venture flops we've never heard of)
You've got one guy who designed all Samsung top shit failing to get his projected 2Gh out of the cointerras for example. Hashfast approached the SHA ASIC game as "this is going to be a piece of piss" and got their fingers burned off to the shoulder.
Anyway, when you've gone out and made a SHA ASIC that came in on time, with power and frequency within even 30% of the theoretical capabilities of the process, then I'll let you tell me how simple SHA ASICs are to make.
This has already been discussed numerous times: only Bitfury used the proper design flow for the mining chip: BSIM (or equivalent analog/mixed-signal) simulation, but this was his first ASIC project. Everyone else used the low-power digital design tools that are emphatically, obviously bad at designing/simulating high-power chips and attempted to saved time by skipping the analog-level design verification.
Thus far all the alleged "top shits" failed to post any substantial technical information. So either they are just CAD monkeys or they knew things are different than promised, but the truth was only available under NDA.
There are many ways (not just leakage) in which immature process could be unsuitable for extraordinary complex chips like OoO CPU or HP GPU, yet sufficient for highly-redundant fault-tolerant designs. My personal SWAG from the available information is that 20nm CMOS processes suffer from random faults and wide spread of parameters so that the transistors aren't really "complementary".