I'm starting to play around with cgminer (Zefir's version from sometime in Jan-Feb, before it was integrated). One thing I noticed was that the HW_RESET was not being done, thus it must be done by hand. No problem there. This next issue however is somewhat puzzling to me:
I set the sysclk to 200000 kHz (200MHz) in the --bitmine-a1-options, the debug output confirms this:
[2014-05-02 07:57:20] Started cgminer 3.9.0
[2014-05-02 07:57:20] SPI '/dev/spidev0.0': mode=1, bits=8, speed=800000
[2014-05-02 07:57:20] spidev0.0: Found 2 A1 chips
[2014-05-02 07:57:20] Setting PLL: CLK_REF=12MHz, SYS_CLK=200MHz
[2014-05-02 07:57:20] Setting PLL to pre_div=2, post_div=4, fb_div=133: 0x88 0x85 0x21 0x84 0x00 0x00
I did my testing between 180MHz and 480MHz, and the temps got as hot as 50C. Now, at 200MHz they get
blazing hot! I can't even touch them anymore.
Is this to be expected? Or is the PLL being misset somehow and I end up running at closer to 800MHz?
Please take a look at latest cgminer driver. The PLL code was re-written to match updated specs quite some time ago and was merged upstream just recently. The issue was a misinterpretation of the PLL formula that got clarified with the latest chip documentation. It affected system clocks below 250MHz, so exactly your case. Please let me know if the problem remains.
As for the chip temps: as soon as the chip starts hashing, it instantly gets very hot. At nominal 800MHz, if you have no top heatsink installed, it reaches almost immediately 60°C with proper back heatsinks and more than that without. Obviously this also highly depends on the supply voltage, which is supposed to be on a safe side over 820mV. This requirement is unfortunately chip specific, so you might find some boards going just fine with 760mV while other are more picky with chips resetting immediately below 820mV.
As for the HW reset: this is always board specific. As reference, please check the A1 board selector sources where reset is performed with different types of i2c board expanders.