Re: Bitcoin puzzle transaction ~32 BTC prize to who solves it
But you'll still need a hall full of GPUs for puzzle 135. 
So, the whole point of this story is pointless without that many graphics cards? Are we just wasting our time and nerves here?
So TSMC responded after 3 months...
Quote
From: ****.*****@*****.****.**
Subject: Re: Inquiry about Special ASIC for secp256k1 Hardware Acceleration
Dear **** ********,
Thank you for reaching out to TSMC regarding your request for a custom ASIC tailored to secp256k1 calculations. We appreciate your interest in creating a specialized chip that includes hardware circuits for modular inversions, batch point additions (using a single inversion), automatic distinct-point detection, and overall hardware acceleration for the Pollard Kangaroo algorithm.
Below is a brief overview of what we can offer and some preliminary information about costs:
Design and Technology Options
TSMC provides a wide range of process nodes, from legacy (180nm/130nm) up to advanced nodes (7nm, 5nm). Choosing the right node depends on desired performance, power consumption, and budget.
We can work directly with your design team or with an external IP partner to integrate the cryptographic hardware blocks required for your application.
Cost Estimates
NRE (Non-Recurring Engineering): This includes design, verification, mask creation, and initial test runs. For a mature node like 28nm, NRE can range from $5–8 million for a moderately complex design, possibly exceeding $15 million if the design is very intricate. For advanced nodes (7nm/5nm), NRE can go beyond $20–30 million.
Per-Wafer Costs: Once the mask set is completed, the cost per wafer varies by node. At 28nm, each wafer might be a few thousand dollars, while at 7nm it could be between $10,000 and $15,000 per wafer. Final unit cost depends heavily on volume and yield.
Production Volume: Higher volumes help amortize NRE more effectively.
Timeline: Typically, after design completion and tape-out, it can take 6–9 months to receive the first wafers for mature nodes, and possibly longer for advanced nodes due to additional verification steps.
Special Requirements for Pollard Kangaroo Acceleration
Adding hardware support for modular inversion, batch point additions, and automatic point distinction detection will require specialized cryptographic IP.
Costs may rise if new IP blocks need to be developed or if advanced security features are required.
TSMC will work with your chosen IP vendor or design partner to ensure the integration and validation of these specialized functions.
Next Steps
To provide a more accurate quote, we would need further details on performance targets (frequency, power constraints), security/certification requirements, estimated production volume, and your target budget/timeline.
Based on your inputs, we can recommend the most suitable process node and give you a detailed pricing breakdown.
Please let us know if you have any questions or would like to arrange a call to discuss technical specifics. We appreciate your interest in TSMC and look forward to working with you on this project.
Best regards,
******* *** *****
Head of Technical Inquiries,
TSMC (Taiwan Semiconductor Manufacturing Company)
Subject: Re: Inquiry about Special ASIC for secp256k1 Hardware Acceleration
Dear **** ********,
Thank you for reaching out to TSMC regarding your request for a custom ASIC tailored to secp256k1 calculations. We appreciate your interest in creating a specialized chip that includes hardware circuits for modular inversions, batch point additions (using a single inversion), automatic distinct-point detection, and overall hardware acceleration for the Pollard Kangaroo algorithm.
Below is a brief overview of what we can offer and some preliminary information about costs:
Design and Technology Options
TSMC provides a wide range of process nodes, from legacy (180nm/130nm) up to advanced nodes (7nm, 5nm). Choosing the right node depends on desired performance, power consumption, and budget.
We can work directly with your design team or with an external IP partner to integrate the cryptographic hardware blocks required for your application.
Cost Estimates
NRE (Non-Recurring Engineering): This includes design, verification, mask creation, and initial test runs. For a mature node like 28nm, NRE can range from $5–8 million for a moderately complex design, possibly exceeding $15 million if the design is very intricate. For advanced nodes (7nm/5nm), NRE can go beyond $20–30 million.
Per-Wafer Costs: Once the mask set is completed, the cost per wafer varies by node. At 28nm, each wafer might be a few thousand dollars, while at 7nm it could be between $10,000 and $15,000 per wafer. Final unit cost depends heavily on volume and yield.
Production Volume: Higher volumes help amortize NRE more effectively.
Timeline: Typically, after design completion and tape-out, it can take 6–9 months to receive the first wafers for mature nodes, and possibly longer for advanced nodes due to additional verification steps.
Special Requirements for Pollard Kangaroo Acceleration
Adding hardware support for modular inversion, batch point additions, and automatic point distinction detection will require specialized cryptographic IP.
Costs may rise if new IP blocks need to be developed or if advanced security features are required.
TSMC will work with your chosen IP vendor or design partner to ensure the integration and validation of these specialized functions.
Next Steps
To provide a more accurate quote, we would need further details on performance targets (frequency, power constraints), security/certification requirements, estimated production volume, and your target budget/timeline.
Based on your inputs, we can recommend the most suitable process node and give you a detailed pricing breakdown.
Please let us know if you have any questions or would like to arrange a call to discuss technical specifics. We appreciate your interest in TSMC and look forward to working with you on this project.
Best regards,
******* *** *****
Head of Technical Inquiries,
TSMC (Taiwan Semiconductor Manufacturing Company)