It is hard to say exactly but most of the improvement (at least in the short term say next 2-3 years) in efficiency is already behind us. The ASIC designers are probably the only ones who have a good idea how much more efficiency they can squeeze out of a design but my guess is there is not that much less.  For a given process node maybe 3x or 4x current performance.   That brings the second factor.  When you shrink the process node (55nm -> 40mm -> 28nm -> 20nm -> 16nm) in general processors gets cheaper,faster, and cooler.  The compound effect of Moore's law.

Bitcoin kinda had a hyper Moore's law effect jumping almost a decade in process node improvements in less than a year.  The first ASICS were at 130nm we are now at 28nm with 20nm being worked on.    That is pretty much "state of the art".  So while slowly chips will move to smaller process nodes (usually a new node every 2 years) we aren't going to see another jump like we did from 130nm to 28nm in a year ever again.

GPU 300 to 500 J/GH
First gen ASICs 10 J/GH
Current best shipping ASICs 0.5 J/GH
Next gen ??  maybe 0.2 J/GH to 0.4 J/GH (improved design @ 20nm)

The gains are going to get smaller and smaller.