Quote zefir:
Step-by-Step Bring-up Process
1) Physical
Most is depicted in the above figure, this is the prose version:

    chip is 1.8V only => use level shifter for all signals from/to host SPI interface
    VDD needs to be ~820-850mV with a max. ripple of 70mV (pilot run chips do not support undervolting)
    AVDD needs to be 1.8V with a max. ripple of 200mV
    power-up PLL settings are based on 12MHz reference clock; if you use a higher value do not start hashing without reducing system clock via PLL or you risk bricking the chip by overclocking it.
    if you have a multi-chip board, use a clock distribution device to drive them with a single oscillator
    heat-sinks on both sides of the chip needed, monitor and ensure surface temperature does not exceed 50°C
    HW reset is mandatory; RSTN needs to be pulled low for at least one second; ensure it was released for at least one second before the first command is issued