That's just my wild guess, I'm not an expert.
If someone already has multi-FPGA board and this board can pump data with 512 bits * 300 MHz rate between chained FPGAs, then development time would be weeks, not months. I expect unrolled implementations of most hash functions to produce one hash value per cycle, and LX150 can run at 300 MHz doing crypto tasks despite high toggle rate, as been proved by Bitfury. Another question - is such data rate between FPGAs possible at all? Well, data transfer doesn't need to be 100% reliable, implementing some error correction code shouldn't take too much LUTs, hashing engine and i/o can sit on different clocks, looks like there are enough diffio pairs in top LX150 variants. Again - anyone with actual field knowledge is welcome to correct me!