UPDATE

Well, it's coming to nearly the end of out first day on this forum, and it's been very interesting.

First of all, thank you to everyone that's taken the time to post on our thread. There's been a fair old mixture and it's obvious that there's many different views about our project and how we're going about it. That's perfectly normal and healthy.

Secondly, thank you to the posters that have taken the time to read right through the proposal and come back with sensible, relevant questions.

Lastly, we really appreciate the numerous emails sent to us wishing us good luck with the project and commenting on how the mining community needs something like this (even if it's not our chip) to compete in the future. It's sad to note that some said they wouldn't post on the thread for fear of being harangued by trolls, but that's the way of things.

As regards the comments about our lack of technical information, it's rather puzzling to us. Give any one of our engineers a die size, process step, power dissipation and hashrate of a mining asic and he'll tell you in about two minutes what it might look like inside. Any competent asic engineer could do the same thing. An SHA256 pipeline mostly contains only three building blocks, namely a full adder, flip flops and a 32 bit fast adder. Yes, there are other gate functions but those three dominate the area and power.

There are few different ways to implement the function as the arithmetic algorithm is fixed. We've saved some gates by using a word expander that generates 2 words per stage instead of one, but that's not particularly original. Where we have saved most area is in the implementation of the full adders and to  lesser extent in the stage flip flops. No matter who asks, we are not going to reveal how we have done these implementations or give nay clues to said - that's our IP and what makes our solution different. What we can tell you is that the power distribution looks like this:

Flip flops : 46.2%
Full Adders (in carry save chain):31.3%
A,E and Word generator Adders: 22.5%

We can also tell you that the area of our full adder is 1.74 square microns, the flip flop is  2.02. The rest of the design information is confidential.


No one has as yet commented about some aspects of our proposal, which we find odd, namely:

- The fact that we have designed our chip to be fault tolerant using extra pipelines as 'spares'

- Our Guaranteed Supply Program to support our core customers

- Our metrics for measuring what price should be paid per GH of capacity over time

So it either means that no one has read about them, or has no comment to make. Are they good/bad/informative/deceptive/wrong/right and soon. Instead there's been constant badgering about who we are.

We expect that most of this comes about from the fact that we come from a corporate environment where individuality is not seen as an asset. We have a different way of approaching sale pitches and projects that is probably somewhat alien to the forum members. Giving you a list of names, companies and accomplishments is totally meaningless because you cannot check if they are accurate or made up. Technical details you can check, and when our engineers saw some of the original specs for power dissipation on competitors chips, they knew they were way too optimistic. Who designed them was irrelevant.

So no, we are not going to give you any other details about our staff. At least we're being up front about it instead of pulling in some guys (and gals) off the street, doing a photo shoot and giving you a load of baloney about their background.

For any competent electronic engineer, our fault tolerance approach should be a dead giveaway as to the environment it came from, as should the fact that we've put a 32 bit microcontroller on each hashing module that will constantly test and rotate the pipelines to ensure data coherency, AND allows them to self test before they get bolted into a machine. That type of system approach doesn't come out of thin air, yet draws no comment, nor does our comments about product engineering.

We also thought long and hard about how we could keep our customers competitive long term. Now if we wanted to scam people, that's not the first thing that we would take any time or effort to consider. We've come up with a way to do it that's original - as a far as we can see no other company has ever suggested anything remotely like it - and it doesn't rely on the customer funding a second round of asic development.

So all in all a mixed bag, but interesting. Please keep the relevant questions coming.

I must also apologise to Spondoolies for even suggesting that they might employ someone to 'represent' them on the forums. It was unprofessional, so sorry guys, good luck with your 28nm chip.