5 ns, that is a delay straight from the 70s. A TTL technology-like delay. Certainly we can do better than that?!?
FPGA fabric frequencies have been stuck around 200-300MHz for 10+ years
because, while the LUTs are still getting (slightly) faster, the wires between them aren't.
So you have to go wider instead of faster.
-rph
As far as I understand, long wires don't come into the picture much when you enter a counter-pattern on the left, let it percolate through 128 stages and then wind up with a yes/no value on the right. Rather, I think the 5ns clock cycle is due to two sequential 32 bit additions, implemented with ripple carries.
The irony is that FPGAs have hardware multipliers (in the DSP blocks), but few or no hardware adders. (I think there is an adder in each DSP block also, feeding into the multiplier, but there are not enough of them.)