nope, no OC by me yet.

If one of my JTAG interfaces is compatable with Altera parts,,,
I'm going to try snooping the FPGA memory thru the JTAG interface.
Low probability of success but interesting.

There may be a way to get past the freq filtr in the FPGA with a raw ASIC request also.
Possibly with a corrctly crafted 'i2cset' command.

If you are just sitting waiting for others to do it,
assume it will not happen.

YMMV


EDIT
MY AVR Dragon (for OC of BFL) and Altera Byte Blaster are compatable with each other.
All I need to do is solder on a 2x5 connector to controller (Jp6).
Here is to hoping the JTAG is still enabled on FW 1.0.
Would not be my first dead end!