I've got a preliminary Nanominer bitstream. I'd like to be clear about whether it works: the digester is functional and has been tested with fpgaminer's code. The rest of it looks fine in simulation, but the final product's *control circuitry* (i.e. state machines) may need fixing. That said, the digester, which is the heart of it all *definitely works* at the size and performance I'm quoting here. To prove this to everyone, I'm linking a .zip with the design files so you can see what I've been working on. I only guarentee the digester (working_sha256.vhd) works 100% but so far the rest looks good.
Also that digester is sitting in for a better, more pipelined one that is smaller and performs better, but is still in the works. I thought I'd let you all see something that actually can produce bitcoin. The *current* specs are as follows:
Note:
-Compiled with Web Edition, I need to go to school and put this through the subscription one
-The fmax *varies* with the chip
-I do not know if this is analogous to Xilinx logic consumption; if it is, things are going well for all of us.
-The code is run preserving nodes with lost fanout because I don't have decent input and Quartus wants to synthesize away the duplicate cores (which are actually working in parallel
-I'm posting this for your interest, peace of mind, and maybe to whet your appetite, this is not to be scrutinized; it's a work in progress. Constructive ideas, go for it, but picking the hell out of my design really won't do much good
-The new core is very promising, I expect a ~15% increase in performance in the next week
So:
Control Circuit Logic Consumption: 289 LC Registers (One per chip)
Core Logic Consumption: 1844 LC Registers (Iterative, as many as you like)
Cycles per Hash: 128
fmax @ Speed Grade 6: 201.73 MHz (Cyclone IV)
Hashrate: 1.58MH/core
--edited to fix size--
So, it's not completely groundbreaking, yet, but there's a lot more where this came from. This little announcement is more to say that I'm working, and this thing is coming. I have my core less than 800 LEs (which would mean a DE0 hashrate of >40MH/s, and a significant improvement past 210MH/s on a Spartan-6), but I need to get timing logistics down, so more to come.
In the meantime, I'll post the VHDL for you all. As always, donations are welcome, I do spend a hell of a lot of time on this and the way things are looking I'll break more records than just the DE0-Nano speed record. I haven't broken the 210MH barrier yet, but soon enough, I just need to put a little more time into it.
Edit: By the way, it's not commented, and it's got an SDC but no QPF or anything, just straight VHDL. All rights reserved me etc.
cheers!
Also that digester is sitting in for a better, more pipelined one that is smaller and performs better, but is still in the works. I thought I'd let you all see something that actually can produce bitcoin. The *current* specs are as follows:
Note:
-Compiled with Web Edition, I need to go to school and put this through the subscription one
-The fmax *varies* with the chip
-I do not know if this is analogous to Xilinx logic consumption; if it is, things are going well for all of us.
-The code is run preserving nodes with lost fanout because I don't have decent input and Quartus wants to synthesize away the duplicate cores (which are actually working in parallel
-I'm posting this for your interest, peace of mind, and maybe to whet your appetite, this is not to be scrutinized; it's a work in progress. Constructive ideas, go for it, but picking the hell out of my design really won't do much good
-The new core is very promising, I expect a ~15% increase in performance in the next week
So:
Control Circuit Logic Consumption: 289 LC Registers (One per chip)
Core Logic Consumption: 1844 LC Registers (Iterative, as many as you like)
Cycles per Hash: 128
fmax @ Speed Grade 6: 201.73 MHz (Cyclone IV)
Hashrate: 1.58MH/core
--edited to fix size--
So, it's not completely groundbreaking, yet, but there's a lot more where this came from. This little announcement is more to say that I'm working, and this thing is coming. I have my core less than 800 LEs (which would mean a DE0 hashrate of >40MH/s, and a significant improvement past 210MH/s on a Spartan-6), but I need to get timing logistics down, so more to come.
In the meantime, I'll post the VHDL for you all. As always, donations are welcome, I do spend a hell of a lot of time on this and the way things are looking I'll break more records than just the DE0-Nano speed record. I haven't broken the 210MH barrier yet, but soon enough, I just need to put a little more time into it.
Edit: By the way, it's not commented, and it's got an SDC but no QPF or anything, just straight VHDL. All rights reserved me etc.
cheers!