Hm, how did you get the number of Logic cells without having a qpf and qsf file?
Why do you design a control logic with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).
I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.
While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me
. So you should recalculate your expectations with the number of 1925 LEs per hasher.
Why do you design a control logic with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).
I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.
While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me
. So you should recalculate your expectations with the number of 1925 LEs per hasher.