I showed the paper to an ASIC designers and the reply was:

"Dual-rail domino logic is glitchy and fickle as f**k, and needs only the slightest excuse (e.g. you put a domino module next to another one) not to work. Clockless logic is interesting, but it's virtually impossible to debug it once you've got your silicon.  You could build the chips, and spend a decade debugging and still have no idea what went wrong"