One could maybe implement some pre-fetching of work and caching of nonces functionality to add the potential 12MH/s - but at the same time maybe the FPGAs need this small idle time to cool down a little bit.
Yes, I also wouldn't worry too much about tweaking this inefficiency out. If a non-throttling 816 unit throttles with 832 firmware (a 2% increase), then that same 816 unit would likely throttle if the 80ms idle time was eliminated.
On the other hand, there's a number of us who are running 896 in cool environments are getting 883 MHash/sec without throttling. Until BFL releases even faster firmwares, we could benefit from this improvement.
The pre-fetch and caching mechanisms has to be implemented by BFL. What can be tweaked SW wise is to reduce the polling time, but this might potentially save only some milliseconds per cycle.
What I am more curious about is the unusually low baud rate used for communication. 9600 Bd was used two decades ago, if we could use today's common rates of 115.2 kBd, that would be a huge improvement potential.
To you Windows folks: could you maybe check if it is possible to change the related COM port settings before you run EasyMiner to e.g. 38.4 kBd 8N1 and check whether they change during and after EasyMiner accessing the BFLS? Thanks.