Bitfury experienced a similar thing.
Yeah, I know
once I have fewer things on my to-do list I think me and him and anybody else interested ought to heckle forums.xilinx.com until they own up to this issue. I have been seeing the very same "center of the fabric drops out first" phenomenon, but until I read about his experiences I had it chalked up to my crappy homemade boards. Now that I'm seeing it on ztex's boards too I am kinda disappointed with X.
Xilinx never designed their FPGAs in such a way that 95% of all flip-flops could switch at the same time.
They just didn't.
Maybe, but they steadfastly refuse to post maximum current ratings for their devices, and say over and over "run our power analysis tools, and if the tool says it's ok, it's ok".
Well, all my designs pass their power analyses. Yet the voltage near the center of the chip is clearly sagging.
Basically, the power analysis tools are effectively "part of the datasheet" and Xilinx has a serious datasheet error here.