Inspector 2211 already mentioned it and it is also hidden in the datasheet ("Simultaneous switching" issue):
Err, isn't "Simultaneous switching" issue about I/O pins? not internal core logic.
Yes, it is -- at least in the Xilinx datasheets (SSO = Simultaneous Switching Outputs).
Could you clarify your comment, ztex? Also, do you have a link to Inspector2211's comment?
The internal GND traces of the S6 seem to be a little bit weak.
I suspect so as well (or that the VCCINT traces are weak). However, any details from Xilinx on this would be useful -- at least an acknowledgement that XPA isn't fully aware of the device's limitations.
According to the Xilinx docs SSO's *does* influence internal logic / other components (especially the MCB). Did you ever asked why?
One possible explanation would be a too large internal GND resistance. If there are large currents (e.g. from I/O's) voltage at internal GND rises to much and voltage between VCCINT and GND falls to much ...