Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?
I'm going to guess that they made the same mistake as the open source designers from another thread.
Since the design is so easy to get functionally correct they didn't bother to create the testbench for simulation and didn't run the full timing simulation.
Then they saved additional time by doing the probabilistic static power estimation, not the accurate power estimation that is driven by the simulation results from the testbench.
I'm also not sure about Altera's licensing and pricing model. There may be an additional license charge for the post-simulation power analyzer.