Phil,
I appreciate the trust. If I remember correctly, you are using the gen 0 board which is the worst case scenario. Since then we have updated part of the layout and the dielectric compound to increase margins!
I have heard from a few source that some of the L3+'s can pull huge amounts of current from 1 or 2 pins within a small amount of time. I would error on the side of caution when using some less than ideal ASIC miners since fault protection cannot detect single pin current draw (that would be incredibly inneficient unless we were maintaining spacecraft or something as equally as critical).
Have you played with those at all?
-Optim