Can you provide the dimensions of the package (important as I am looking into immersion cooling so critical heat flux is important)?
Overall, our chip most closely resembles a modern "hot CPU" design (Intel Sandy Bridge E, AMD FX-9, SPARC T4, etc.). The package is a BGA, 45mm x 45mm external dimensions. The total die area is approximately 324mm^2. The die is split in 4 - i.e. under the metal lid there are 4 dies in a square arrangement, each approx 9mm x 9mm with 5mm gap in between each one (for better heat dissipation and spreading).
One highly relevant feature regarding power use is that the GN chip incorporates on-die temperature sensors and a control system designed to adjust voltage and clock speed to the capacity of the cooling system. Thus if the cooling system can dissipate a greater amount of heat, the software can "overclock" the chip to fit it's power usage to the heat dissipation capacity, and produce greater hashing capacity.
Similarly, the chip will "underclock" itself in response to external circumstances that reduce the available heat dissipation capacity (say, a very hot day, a failure in the cooling system, a blocked air vent...). The overall design intent is for the chip to always operate at the maximum possible hashrate dictated by the circumstances.
Finally, one recent piece of news is that we have received results for the stage-III thermal test (full physical prototype) from our cooling system partner. Stage III tests involve the creation of a full and complete prototype of the system, including the same case, fans and cooling system that will be used in the Baby Jet as shipped. The only difference is that the chip is substituted by a variable-output heating element with the same form factor as chip. The test consists of running the Baby Jet as if in production, and increasing the wattage produced by the heating element while monitoring temperatures.
Can you clarify that the nominal wattage of the chip itself is ~250W and the wattage of the system at the wall is ~350W? Both numbers have been used but it isn't exactly clear what they represent.
At the nominal operating point (400Gh/s) the best silicon will consume ~250W according to our simulations. There is some variation in silicon however, so some silicon will consume a few % more. This power level is at the chip only. The system has 2 power conversion stages between the wall plug and the chip - first an ATX power supply that outputs 12v. This supply is about 88% efficient. Then there is a second supply stage on the module board the chip is mounted on. This second supply stage converts the 12v down to approximately 0.7-0.8v that the chip runs at. The combination of the losses in both PSU stages and the additional consumption from the pump, fans, controller etc account for the difference between the 250W at the chip and about 350W at the wall.
Can you provide the dimensions of the ASIC board? Estimate is fine. Can you also provide an estimate of the height of the tallest board component (excluding waterblock)?
The module board is ~4" wide and approx 10" long (may end up a little longer, up to 12" - we are still configuring the power connectors). Here is a draft layout - note this is not final and is subject to change. Dimensions in mm.
https://hashfast.com/wp-content/uploads/2013/09/draft-layout.gifThe tallest board components are two conventional air cooled heatsinks on the FETs that form part of the power supply. I don't have the height to hand - I will get back to you. Here is a rendering of a draft of the module boards, installed in a Sierra. Note - this design is not final, and is subject to change.
https://hashfast.com/wp-content/uploads/2013/09/ISO-RENDERING-1.jpgCan the controller handle more than 1 hashing board? If so is there an upper limit? 4 boards? 10 boards? 50 boards?
Yes - the controller (which is a raspberry pi) should be able to control many boards. We have not analysed how many. Our chip has been designed with a particularly advanced internal interface, and supports variable difficulty levels and n-time rolling on chip. This massively reduces the traffic from the controller to the chip, keeping the CPU requirements on the controller very low. The interface supports daisy chaining up to 63 chips to a single serial port on the controller. The traffic levels and limits will depend on the difficulty levels the chip is configured to run at, and the use of n-time rolling.
Will you consider selling just ASIC boards instead of complete systems?
Yes - we plan to add complete module boards to our website shortly. These can be directly controlled via either a serial port, or USB. We will be open sourcing the drivers in CGMiner.