Thank you for the tip on the $99 fpga training kit. I was considering something like this myself and this is actually very useful. Can you recommend any sources of information on how mining is be achieved on an fpga?
Start with something simple like SHA256D used in Bitcoin:
https://github.com/progranism/Open-Source-FPGA-Bitcoin-MinerOr something from the official Xilinx marketing publication:
http://issuu.com/xcelljournal/docs/xcell_journal_issue_84/16Have fun!
Edit: I forgot to include standard explanation about the difference between CPU programming and FPGA programming.
CPUs have von Neumann architecture with linear memory, e.g. from 0 to 4294967296. Compiling and running your first 10 line program will take seconds on your typical usable computer with 4GB of RAM.
FPGA have a completely generic two dimensional architecture that literally has kajilion of constraints. Most of those constraints are secret to the FPGA vendor. The XCVU9P FPGA discussed in this thread has about 2104 pads, just describing the pads that are actually connected with useful signals on the VCU1525 board is a file that has 25 pages in the manual. Those are the constraints that are visible and not secret.
When compiling your first 10 line FPGA program the Xilinx toolchain will still have to process those constraints even if you use less than 1% of 1% of the whole VCU9P chip. On the other hand the small XC7A35T chip on the training board has much, much less internal constraints that needs to be read by the toolchain.
You will observe that your small 10 line FPGA program will be completely compiled and done for a small device like like 7A35T while for the large device the Xilinx toolchain is still decrypting the secret VU9P constraints file. Amazon recommends that you run their FPGA development kit for VCU9P on a computer with 32GB of RAM to get sensible performance for nontrivial programs.
Just be aware of the above.
Edit2: Trying to learn logic design on a high-end device may seriously test your patience. Start with a low-end device.
Edit3: Grammar fixes.
I highly recommend Altera/Intel Quartus over Vivado for learning, despite using Xilinx for all my professional projects. Quartus requires less patience and is easier to fool around with. Get a Max10 dev kit, super easy way to test a lot of basic designs and you can fit one pipeline for most small things.
SHA256 is actually imho harder than some of the SHA3 competition candidates. Keccak is actually pretty great as a first run - it can take about 2500 luts to implement a none-pipelines single round version. Getting enough UART Comm running to meaningfully get bits to hash on/off the chip takes more effort.
I validated my Keccak RTL on a Max10 using Quartus simply because it could be done so easily and relatively quickly. Adapting and filling out all the pipelines on the VCU118 (Ultrascale+ Virtex VUP9) takes hours to synthesize route and place for every minor change on a very wel equipped development box. The Artix 7 200T version takes about 35 minutes a shot on my MacBook Pro (in a VM). Patience is the name of the game - or set web dev and app skills aside and actually spend some serious time planning and doing pencil + paper design validation and review, then use logic simulation and ultimately timing simulation before even putting anything on a chip.