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Showing 3 of 3 results by quocthanh1302
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Topic
Board Announcements (Altcoins)
Topic OP
[ANN] PerFix - Trusted & Secure Crypto Project (POW+POS)
by
quocthanh1302
on 06/05/2023, 06:59:03 UTC

https://i.ibb.co/Lx7pwxX/Screenshot-1.png


Specifications

Name                PerFix
Symbol                PFX
Launched                01-04-2023
Version                v1.5.0
Language                C++
Hash algorithm        ProgPowZ
Consensus                POS + POW
Block time                1 minute
Block reward        10 PFX
Maximum Supply    8 (uncapped)

Explorer

        https://explorer.perfix.io             

Wallet

https://github.com/PerfixCoin/Perfix/releases/download/v.1.5.0/Perfix_v1.5.0.zip

Exchanges

https://xeggex.com/market/PERFIX_USDT

Trusted & Secure Crypto Project

PerFix is a technology that seeks to combine the latest advances in digital finance, decentralized applications and artificial intelligence.
The security of your transactions is ensured by the time-tested CryptoNote protocol. The hybrid POW and POS consensus algorithm makes it possible for anyone to mine and use PerFix.

How to start?

Choose your wallet
To start using PerFix, first of all, you will need a wallet. Visit our downloads page and choose the wallet that suits you.
There are PerFix wallets for different platforms that provide everything you need so that you can start using PerFix right now.

Get some coins
After the wallet is installed, you will need to put some coins into it.
You can use mining to get PerFix coins or buy PFX on a cryptocurrency exchange.

PerFix principles

Safety
Users must be able to trust PerFix for the security of their transactions, without the risk of errors or attacks on the network. All transactions are cryptographically secured using
the latest and most efficient encryption tools.

Privacy
PerFix takes the privacy of its users seriously. The highest level of privacy must be available to all users without exception, whether they are technologically competent or have no idea
 how cryptography works. A PerFix user should not feel pressure on their habitual rhythm of life and their expenses due to the risk that other users may find out about them.

Decentralization
PerFix aims to provide the maximum degree of decentralization in both network security and code development. The hybrid POW and POS consensus algorithm prevents specialized
 mining hardware (ASIC) from dominating the network and allows for a fair distribution of rewards for finding new blocks. In addition, development and research are carried out within
 the framework of global cooperation and are carried out with maximum transparency. Each development decision is open to public discussion and voting.

PerFix development and research
Subnet, smart contracts and decentralized applications
PerFix is launching a subnet and its own Gas Token PFXT on the Avalanche platform, this will enable the project to scale. PerFix users will be able to implement fast smart contracts for
decentralized applications with configurable fees and other benefits of the Avalanche network. To pay for Gas, users do not need to purchase an additional asset, all transactions will be
 made with the PFXT token. To convert PFX for the PFXT token, an autonomous decentralized exchange office will be launched.

Neural network and artificial intelligence
Inspired by the successful experience of fellow programmers, PerFix begins research aimed at launching a neural network. Artificial intelligence successfully copes with some tasks,
 including helping users with code generation. Artificial intelligence that will generate the smart contract code in the Go (programming language) is the goal of our research! In our
opinion, this technology will give a large influx of new users to the sphere of the blockchain and will make it easier for developers to perform some tasks.





Post
Topic
Board Mining (Altcoins)
Re: TRULY Custom RAM Timings for GPU's with GDDR5
by
quocthanh1302
on 06/03/2017, 09:22:37 UTC
Code:
MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
TRCDW    4:0 5bit    Number of cycles from active to write
TRCDWA   9:5 5bit    Number of cycles from active to write with auto-precharge
TRCDR  14:10 5bit    Number of cycles from active to read
TRCDRA 19:15 5bit    Number of cycles from active to read with auto-precharge
TRRD   23:20 4bit    Number of cycles from active bank a to active bank b
TRC    30:24 7bit    Number of cycles from active to active/auto refresh

#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14     4 bits

#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18      7 bits


MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
TNOPW    1:0 2bit    Extra cycle(s) between successive write bursts
TNOPR    3:2 2bit    Extra cycle(s) between successive read bursts
TR2W     8:4 5bit    Read to write turn
TCCDL   11:9 3bit    Cycles between r/w from bank A to r/w bank B.
TR2R   15:12 4bit    Read to read time
TW2R   20:16 5bit    Write to read turn
----   23:21 3bit    Unused.
TCL    28:24 5bit    CAS to data return latency


#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4     # 5 bit

#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9    # 3 bit

#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000    # 4 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc     

#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000  # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10

#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18


MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63

TRP_WRA   5:0  6bit   From write with auto-precharge to active - 1.
----      7:6  2bit   Unused
TRP_RDA  13:8  6bit   From read with auto-precharge to active - 1.
----    16:14  3bit   Unused
TRP     19:16  4bit   Precharge command period - 1.
TRFC    26:20  7bit   Auto-refresh command period - 1.
TCKE    31:28  4bit   CKE power down exit timer.

#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f     
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0        # 6 bit
 
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8        # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf            # 4 bit

#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14          # 7 bit

# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING
can you show structure MISC2 in bits like RAS CAS MISC above, thanks.
Post
Topic
Board Mining (Altcoins)
Re: RX480 (Reference) 31+Mh, Custom Rom
by
quocthanh1302
on 24/08/2016, 03:51:34 UTC
ok finally got the rom to work, had to do a full re-install of the drivers , copy the modded driver and then boot with option 7

not sure how to get option 7 to auto load on boot.

One issue I'm seeing

dual mining seems quite neutered compared to stock ? at 30 dcri I am seeing 24.5 eth and 360ish sc when before I was getting 23.5 eth and 420 sc

now if I mine eth only I was seeing high hash rates around 31mhs

Also the cards all now detect and 4GB I know others mentioned that as well, it does seem  that the core clocks are maxing around 980 which might be the reason for the low SIA or dual mining ?

Try this one Marvell, 29Mh otb, low power usage


Greetings
thanks Marvell1 and Eliovp!
I have HIS rx 480 custom 8gb. Can I to use this room for it?
thanks very much.