We have designed a next generation bitcoin mining solution and we are offering the IP (Intellectual Property) for sale.  The design is currently running in System Verilog RTL and we have done a number of synthesis runs and power simulations to have a good feel for where our performance will lie:

• Performance  ~256 GH/s per die
• Power          < 32 Watts per die
• Price            < $32 per die (packaged and tested)
•                   < $0.125 per GH/s

These are of course preliminary and dependent on the foundry selection.  We are assuming a 28nm fab.  We can also change the number of cores to suit customer requirements.

We have done extensive research into how to minimize the power and reduce the combinatorial and sequential switching per cycle.  The numbers we are quoting, we believe, are conservative and with some more effort we can reduce these numbers further.  These numbers are nominal figures and are not representative of the values achievable from overclocking.

We have chosen a foundry partner and our estimates are based on using that foundry but we are open to go to any foundry that can support us.

As part of this IP sale we would expect to be involved all the way through the manufacturing cycle.  In fact we are happy to entertain a number of engagement options from and outright sale, a partnership or using us as an OEM supplier.

We have over 30 calendar years of experience (not a collective number of years, that for us would be centuries) in ASIC design and have designed many very large ASICs for high performance computing.

We are interested in serious inquiries only.  There are a number of other features that we have incorporated into our design that we believe will provide a significant gain over the competition.  We will only discuss these under NDA (Non-disclosure Agreement) with parties we have screened.

This was originally a Newbie post but I got no answers.  Anyone?

OK so while we wait for the physical design guys to get back to me with area and power I'm looking at how to hook up so many cores in parallel.

I have a question or two:

Is there a preferred method of splitting the workload ?

Can I partition the nonce and have each core work and a subset?

Should all cores work on the same job at once?

How do Avalon, BFL and multiple GPUs etc. do it now?

Simple.  I have a minimum buy of 25 wafers.  That amounts to something like 100,000 chips.  Sure I could build a system with a thousand chips but I'm not likely to build 100 for myself.  Besides from what I read that many chips would need to be spread out across the network to keep the balance.  Wouldn't want to spoil the whole thing.

Can anyone answer my questions??

Lost that question mark.  Sorry, guess I really am still a Newbie!!

OOPS that second question should be:

Can I partition the nonce and have each core work on a subset?

OK so while we wait for the physical design guys to get back to me with area and power I'm looking at how to hook up so many cores in parallel. 

I have a question or two:

Is there a preferred method of splitting the workload ?

Can I partition the nonce and have each core work and a subset?

Should all cores work on the same job at once?

How do Avalon, BFL and multiple GPUs etc. do it now?

Well I'm encouraged by the interest even if this still in the Newbie area!

The power optimization step is so we can judge how many cores to put on a single chip.  You wouldn't want the thing melting after all!  This design is mostly flip-flops which use most of the power in a chip so we need to careful here to get it right!

As far as pre-orders go I think we are too early, but assuming this thread persists then I guess an order is established as long as they pay up when required.  At least it can be an order for rights of refusal.

Well trial place and route looks good!!

Timing comes in around 711ps so I'll fudge that to 800ps.  So we should get a clock rate of 1.25 GHz.  So our core will run at 1.25 GH/s.

So now we will investigate power and area to find the optimal number of cores we can package in a single die (chip)!

I'd like it to be 8 so we have a 10 GH/s chip!  100 chips 1 TH/s

It seems that this whole community has been bitten by poor performance from so called ASIC suppliers.  I does make me pause to consider if I want to get into this but the potential is intriguing.  We certainly know how to build ASICs and assemble them onto boards and manufacture them.  We are also hooked up with a number of Contract Manufacturers (CMs) who could manufacture in volume and then build and ship to order.

So I'm going to look into this further and see what happens! 

Our trial place and route is nearly done so will post the results shortly!

Shipping product is only really a function of planning and experience.

Too soon to talk of price but this looks like a fairly small chip, to us at least.  So the manufacturing cost should be very low.

I've been looking at the Bitcoin community for about two weeks now.  This started as my company has received numerous requests for an FPGA or ASIC solution for bitcoin mining.

   My company is a small design house that primarily designs ASICs, but also some FPGA and PCB level products.  We have even done a fair amount of small quantity production.  All of our engineers have 20 to 30 years of experience in design and development and we have collectively, successfully completed over 40 ASICs and many FPGAs and system level products.  Personally, I am a former VP of engineering for a supercomputer company and an accomplished processor architect.

   So just for kicks and chuckles I coded up my own SHA256 engine and built a bitcoin miner.  My first effort was to push the design through the Xilinx design tools and see where we stand.  I decided to only use the main fabric of the FPGA (no DSP or Block RAM) so that the design will easily translate into an ASIC later.  Here are my results:

   Xilinx Kintex 7   XC7K160-1   400 MH/s  at 10.12 Watts
   Xilinx Kintex 7   XC7K160-3   500 MH/s  at   9.81 Watts

   Those power numbers suggest that I could push the -3 version faster.

   Interesting but it seems that the community needs ASICs.  So we are doing a trial place and route of this verilog design in our ASIC tools to see where we are with an ASIC.