I am interested in trying my hand at creating yet another FPGA cluster hasher, with each cluster connected via a single USB connection to the host (rather than 1 per FPGA).

I've looked at the Cairnsmore 1, Ztex, and Icarus drivers; each one has hard-coded some of the idiosyncrasies of those particular devices.  I'm wondering if there is something like a generic CGminer driver skeleton I could fill in / develop against.

Is there a simple block of code that easily links with CGminer, passes up the relevant info from the device chain (estimated duration of one hash-cycle iteration, number of hashes completed per cycle) to the main miner program on initialization, downloads base header data and range to be hashed against from the miner to the device with each getwork or stratum fetch, receives proof of work from the device to send to the mining pool, and sends an interrupt to the device when assigned work becomes invalid?

Given the proliferation of mining devices, there's almost a need for a "miner driver" specification just like the old "packet driver" specification back in the days of Win32s enabling Win3.11 to connect to the internet, so that the people creating the new mining devices would be responsible for driver creation, rather than the mining stack software creators.

Thanks,
 -Tom

I am interested in trying my hand at creating yet another FPGA cluster hasher, with each cluster connected via a single USB connection to the host (rather than 1 per FPGA).

I've looked at the Cairnsmoore 1, x6500, and Icarus drivers; each one has hard-coded some of the idiosyncrasies of those particular devices.  I'm wondering if there is something like a generic BFGminer driver skeleton I could fill in / develop against.

Is there a simple block of code that easily links with BFGminer, passes up the relevant info from the device chain (estimated duration of one hash-cycle iteration, number of hashes completed per cycle) to the main miner program on initialization, downloads base header data and range to be hashed against from the miner to the device with each getwork or stratum fetch, receives proof of work from the device to send to the mining pool, and sends an interrupt to the device when work becomes invalid?

Given the proliferation of mining devices, there's almost a need for a "miner driver" specification just like the old "packet driver" specification back in the days of Win32s enabling Win3.11 to connect to the internet, so that the people creating the new mining devices would be responsible for driver creation, rather than the mining stack software creators.

Thanks,
 -Tom

I've been struggling for 2 weeks trying to get the Tricone Mining Logic running on a Lancelot (updated Icarus) board.  This has 2 Spartan 6 LX150 chips, with a 100MHz clock on J1.

I've identified (and I think fixed) a big hole in the URjtag implementation for the USBBlaster cable (pod bit-banging commands to set TMI/TCK/TMS weren't implemented), but am still having difficulties getting it to run.

I'd like to duplicate someone else's working implementation and then work backwards. 

Has ANYONE been able to get the current TML bitstream (maclane) to run on a Lancelot board with a USB Jtag interface, and if so, which/whose JTAG interface did you use?

Thanks,
 -Tom