Quote from: Puppet on January 21, 2014, 01:00:18 PM

Quote from: VinceSamios on January 21, 2014, 08:36:47 AM

Quote from: Bargraphics on January 20, 2014, 10:48:18 PM

Q. What went wrong with the RTL?
A. I didn't get a direct answer with this other than delays were made to make better decisions about what direction the company would take due to competition and bitcoin price.

The difficulty rise was too rapid and manufacturers started offering very efficient 28nm products at $3/GH - Ken realised Nextreme chips were too expensive to manufacture and too inefficient on power. The right decision was to switch to Easicopy, and this is the decision I believe Ken made. I've been saying it for a while now, quote me on it later.

If this is the case, people should be extremely impressed with the companies ability to "turn it up", and ken's guts to take this step despite the fallout we're seeing on the forums.

You are overlooking one crucial element : timing. Easycopy as I understand is a full mask set process, like any other asic. Tape out process would be pretty much identical too, and therefore if the RTL is only finished just now, and even assuming eASIC has some magic software to synthesize an RTL in to a GDSII by pressing a button, it will be months before that results in actual chips.

OTOH, nextreme should in theory allow at least samples in a very short amount of time (especially ebeam samples, but even single mask wafers ought to be lot faster). So even if those chips are less power efficient and (far) more expensive, I doubt it wouldnt be worth it. We are no where near the point yet where asic production cost is an issue. I do agree that Easycopy should be developed in parallel for when that happens, but I see no reason to halt nextreme chips unless for whatever reasons, these cant be manufactured within a short order either. Which would point to eASIC nextreme 3 not being ready.

Vince says we switched from Nextreme to Easicopy, Puppet says we should do Nextreme with Easicopy happening in parallel for later.

I would like to draw everyone's attention to the following diagram (pay close attention to the first step in purple, as it's a requirement for both approaches):

According to Ken, we have hired the most competent RTL design team and the RTL problem has been solved.

This should mean that we are almost able to move on to the "Convert FPGA & Timing to eASIC nextreme" step in the diagram above, if not already.

Now, I want to draw everyone's attention to this quote from an official press release in 2005:

Quote from: http://www.easic.com/easic-technology-helps-stmicroelectronics-achieve-a-landmark-24-hours-from-rtl-to-tapeout-using-easics-innovative-configurable-logic-technology

STMicroelectronics achieved 24 hour turnaround from RTL to tape-out using eASIC’s Structured eASIC technology. ST’s engineering team was able to ship the final GDS-II files to the silicon fab for eBeam customization in less than a day from the time RTL was received. The eBeam customization, which is maskless, takes only a few hours for Structured eASIC devices since just a single Via layer needs to be written.

As you can see (from the press release and diagram above), eASIC's technology allows very fast turnaround from where we are now (the RTL stage) to where we want to be (the tapeout stage).

The tapeout itself takes time as mentioned by Puppet - possibly days to weeks in the case of Nextreme digital structured ASICs, and weeks to months in the case of Easicopy cell-based ASICs.

As such, the wisest move would probably be to do both, in parallel, but only after checking some samples work (Nextreme).

Normally companies wait until producing 300,000 to 900,000 chips, but we probably already have the funds required with current BTC/USD price:

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