Quote from: fpgaminer on May 09, 2013, 12:27:46 AM

Quote

Thanks for you hint. I've already tried SmartXplorer with default 7 built-in strategies, but can't achieve above 160MHz result. so, you mean I should use the cost table method to brute force it? thanks.

Yup. For reference, the released bitstreams took days/weeks to compile.

xbaby,

You can also try to floorplan the DSP48s if you want to cut your runtime. To get the boards I have with V6 130Ts to run at 300 MHz, I had to constrain each of the DSP48s, otherwise there was no chance. This was based on the original verilog port, but I'm sure the problem with no pre-placement is the same.

iidx

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