Quote from: MrTeal on January 07, 2014, 07:42:34 PM

Quote from: zefir on January 07, 2014, 06:48:30 PM

The queue was required for the very first sample chips with limited availability. Following waves will be available in volumes and should not need to register.

As for the clock: the eval board in China uses 12MHz clock, Bitmine's 16MHz - both work. PLL settings allow arbitrary setting of divider, configuration tables for the PLL settings for 12 and 16MHz input clock and different system clock rates will be added to the documentation ASAP. If you design a multi-chip board, to feed all chips with one oscillator you need - guess what - clock buffers (no kidding here).

Cheers,
zefir

Crap, that means another 6 months until we get chips.

I think he means you need clock buffers on the board, not on the chips. No need to worry yet.

Edit: Removed excess text.

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