Hello,

I've managed to get access to a Spartan6 150 FPGA board and Xilinx toolset at work at lunch/evenings to play with. The idea is to learn VHDL, which is going OK. I'd really like to have a play with Bitcoin too.

I hope there is someone here that can help me with regards to TheSeven's Xilinx VHDL implementation. If not, do you know where can I get help?

I've looked back through this topic and have seen something similar, but the response didn't help me. When I synthesise the project, I get the following message for every stage (i.e. If DEPTH = 0, I get it once. If DEPTH=6, I get it 64 times).

Quote

Xst:3031 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.

I think the problem is caused by the following code in sha256_pipeline.vhd;

Quote

rounds: for i in 0 to 2 ** DEPTH - 1 generate
   signal round_k : std_logic_vector(31 downto 0);
   signal round_w : std_logic_vector(511 downto 0);
   signal round_s : std_logic_vector(255 downto 0);

begin
   round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));

My understanding is that round_k is not set on a clock pulse, and therefore gets treated as asynchronous. The result of this is that a fully unrolled (DEPTH=6) implementation does not fit on the 150 device (I've read it should).

What am I doing differently to everyone else? I haven't seen mention of any errors/warnings/info by others that have used the code.

In addition, are there any warnings that I should expect to see? (I also get warnings that txdata/txwidth will be optimised away - although I haven't looked at that code in detail yet).

The only difference between the download and what I'm running is that I've had to change the DCM (I created a new one using CoreGen as the old one generated errors).

Thank you very much for any help.

LateToTheParty

Posts

Merits