Quote from: DeathAndTaxes on July 25, 2012, 08:48:38 PM

Quote from: eleuthria on July 25, 2012, 08:19:11 PM

We have a good guess. They claim their 3.5 GH/s chip is USB powered. So there you go. 1400 MH/watt (or better), which means if the 1 TH/s Rig is using the same chips in parallel, 714 watts.

This 130nm shared wafer research ASIC can achieve 140 MH/J performing SHA-256 on a streaming input.

http://rijndael.ece.vt.edu/sha3/index.html

Keep in mind:
a) this was designed as a testbed for SHA-3 and runs at only 50 Mhz. Not exactly ideal for SHA-256.
b) it is on a 130nm platform. 65nm would be roughly 4x the MH/J. 45nm would be roughly 8x the MH/J
c) VT own data shows the chip can easily run at much higher clock speed without increasing the gate count.
d) the design is optimized for multi-round hashing which is ill suited for Bitcoin (where single nonce header is hashed once, check and discarded or returned).
e) it was designed as research project at my alma mater Virgina Tech (hardly ultra cutting edge fabrication).

Despite all those handicaps this unoptimized (for Bitcoin hashing) ancient 130nm multi-purpose shared wafer chip built at a university research fab can achieve 140MH/J. With optimization and a modern 45nm process >2 GH/J is certainly "possible".

Once again before you misinterpert. I am not buying a BFL product (or any mining hardware). I don't really care if BFL has the greatest hasher on the planet or the best scam. I agree it is foolish to give money upfront and hope for the best. All that being said you undermine your argument when you claim the possible is impossible.

Is a 3.5 GH/s ASIC running on 3.5W possible? Most certainly.
Will BFL produce it (and on time, and on spec)? Who the frack knows.

Are you sure that's right? They listed 13.76mJ/Gbits. A double SHA-2 would be 1024 bits, so it should be about 70MH/J. That's a long way from 1000MH/J. Possible with a more advanced process and a better design? Maybe. That design also had the SHA-2 portion of the chip being 0.125mm^2, obviously not including wire pads and whatnot that would also be needed on BFL's chip.

They ran that at 200MHz for a max Tp of 1.51Gbps. Guo's seminar paper also stated that the static power of the ASIC was <1%, so let's assume we can scale power linearly with clock speed. Let's assume that design optimizations can cut the area and power use by half for the same single SHA-2 round. That would give us 0.0675mm^2 for a round and 2.56mW @ 50MHz, giving 369kH/s (BTC double SHA-2). Let's say we can scale this up to 1GHz with no increase in voltage and a straight linear increase in power and hashing. That's now 0.0675mm^2 with 51.2mW and 7.37MH/s per round @1GHz. To get 3.5GH/s out of one chip, you'd need 475 such rounds, giving a die size of 32mm^2 and power use of 24.32W.

Now, if they went 2 full nodes down to 65nm, and really did go full custom instead of standard cell and could do maybe a 5x improvement over the VT design, I could see BFL's numbers being reasonable. That's a huge huge leap though, a full custom 65nm design would not at all be cheap to produce.