I really think many are over estimating what a 45nm ASIC is capable of.
This is math. Power consumption varies with the square of the feature size. So when comparing a chip designed at 45nm to a 130nm version of it running at the same frequency and same voltage, there should be a 8x better power efficiency: (130/45)**2 = 8.3
Ask your dad, he will tell you that for 2 identical designs, power consumption will vary proportionally to the transistor junction area.
I'm aware of the mathematics, the math of scaling does work like that. But it's not the only math that effects the final outcome.
However you have also made a convenient assumption that it will utilise two usb ports to power it, allowing it to have twice as much power, for a max of 5 watts. That is abit of a stretch to assume that and why the math to me does not add up for it to do 3.5 Gh/s at 2.5W and is what I stated.
2.5W is also something an ASIC could easily run off, it would not need to rely on 5W to work fully. 5W might allow it to go that bit higher, but I still think it be off by a bit of course.
Their FPGA to ASIC conversion and how efficiently they move that over will matter the most, since few are doing the same sort of double hashing, so it's not like they can just copy or modify the design of someone elses.