Quote from: pieppiep on July 29, 2012, 02:15:46 PM

For those who are not following Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)

Quote from: friedcat on July 29, 2012, 01:39:29 PM

Update

Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.

Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W

Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.

Fixing the url for you. Interesting numbers at 130nm, very promising as well for the future of ASIC development.
So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.