Quote from: miguelmorales85 on March 20, 2015, 02:05:21 AM

Quote from: zvisha on December 09, 2014, 12:53:02 PM

Some explanation about ASIC stats (per clients request.)

[uptime of minergate and fpga version]
Uptime:6457 | FPGA ver:62
[this PSU not in power or not recognised]
-----BOARD-0-----
PSU[UNKNOWN]: 0->(11w/11w)[11 11 11] (->11w[11 11 11]) (lim=1275) 0c 0GH cooling:0/0x20000000
[this PSU intake 1346w, output 1274w. Last 3 measurements show 1272,1274 and 1258, board rate=2176GH]
-----BOARD-1-----
PSU[NEW-MURATA]: 1346->(1274w/1274w)[1272 1274 1258] (->1222w[1221 1221 1222]) (lim=1275) 0c 2176GH cooling:0/0x20000000
[Those loops (top) have no power. Most probably PSU disconnected]
LOOP[0] OFF TO:0 (test serial failed or something)
0: disabled (i2c BAD, btw!)
1: disabled (i2c BAD, btw!)
2: disabled (i2c BAD, btw!)
LOOP[1] OFF TO:0 (test serial failed or something)
3: disabled (i2c BAD, btw!)
4: disabled (i2c BAD, btw!)
5: disabled (i2c BAD, btw!)
LOOP[2] OFF TO:0 (test serial failed or something)
6: disabled (i2c BAD, btw!)
7: disabled (i2c BAD, btw!)
8: disabled (i2c BAD, btw!)
LOOP[3] OFF TO:0 (test serial failed or something)
9: disabled (i2c BAD, btw!)
10: disabled (i2c BAD, btw!)
11: disabled (i2c BAD, btw!)
LOOP[4] OFF TO:0 (test serial failed or something)
12: disabled (i2c BAD, btw!)
13: disabled (i2c BAD, btw!)
14: disabled (i2c BAD, btw!)
[ Those are bottom loops ]
LOOP[5] ON TO:0
[ This DC2DC configured to 682mv, but actually provides 679mv. The limit of the voltage is the minimum of DCl (DC2DC limit), Tl (temperature limit) and Ul (userset limit). The DC2DC limit and temperature limit are learned durring the runtime, but forgoten every 3 hours for case of environment temperature change. The ASIC pulls 68 watt, 92 amper and the DC2DC temperature is 59c. The ASIC is bellow 90C, while the top limit is 120c. The freq` is 710MHz, the limit FOR THIS VOLTAGE FOR THIS ASIC is 710MHz. it found 226 shares, and it has 193 functioning engines. The other flags are not important.]
15: DC2DC/1/:[vlt1:679 vlt2:682(DCl:794 Tl:794 Ul:749) 63W 92A 59c] ASIC:[ 85c (120c) 710hz(BL: 710) 226 (E:193) F:0 L:0]
16: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 66W 97A 62c] ASIC:[ 85c (120c) 745hz(BL: 745) 220 (E:192) F:0 L:0]
17: DC2DC/1/:[vlt1:679 vlt2:682(DCl:794 Tl:794 Ul:749) 59W 87A 54c] ASIC:[ 85c (120c) 675hz(BL: 675) 191 (E:193) F:0 L:0]
LOOP[6] ON TO:0
18: DC2DC/1/:[vlt1:679 vlt2:682(DCl:794 Tl:794 Ul:749) 66W 97A 62c] ASIC:[ 85c (120c) 735hz(BL: 735) 246 (E:192) F:0 L:0]
19: DC2DC/1/:[vlt1:679 vlt2:682(DCl:794 Tl:794 Ul:749) 62W 91A 66c] ASIC:[ 85c (120c) 715hz(BL: 715) 232 (E:193) F:0 L:0]
20: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 66W 97A 71c] ASIC:[ 85c (120c) 760hz(BL: 760) 240 (E:193) F:0 L:0]
LOOP[7] ON TO:0
21: DC2DC/1/:[vlt1:679 vlt2:682(DCl:794 Tl:794 Ul:749) 64W 95A 74c] ASIC:[ 85c (120c) 735hz(BL: 735) 225 (E:193) F:0 L:0]
22: DC2DC/1/:[vlt1:679 vlt2:685(DCl:794 Tl:794 Ul:749) 67W 99A 78c] ASIC:[105c (120c) 765hz(BL: 765) 227 (E:193) F:0 L:0]
23: DC2DC/1/:[vlt1:677 vlt2:685(DCl:794 Tl:794 Ul:749) 67W 99A 65c] ASIC:[105c (120c) 740hz(BL: 740) 235 (E:193) F:0 L:0]
LOOP[8] ON TO:0
24: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 71W 105A 72c] ASIC:[110c (120c) 775hz(BL: 775) 210 (E:193) F:0 L:0]
25: DC2DC/1/:[vlt1:681 vlt2:682(DCl:794 Tl:794 Ul:749) 66W 96A 81c] ASIC:[110c (120c) 770hz(BL: 770) 240 (E:193) F:0 L:0]
26: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 69W 101A 83c] ASIC:[105c (120c) 795hz(BL: 795) 225 (E:193) F:0 L:0]
LOOP[9] ON TO:0
27: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 70W 102A 85c] ASIC:[110c (120c) 795hz(BL: 795) 246 (E:193) F:0 L:0]
28: DC2DC/1/:[vlt1:677 vlt2:682(DCl:794 Tl:794 Ul:749) 66W 97A 85c] ASIC:[110c (120c) 775hz(BL: 775) 236 (E:191) F:0 L:0]
29: DC2DC/1/:[vlt1:677 vlt2:680(DCl:794 Tl:680 Ul:749) 70W 104A 72c] ASIC:[115c (120c) 785hz(BL: 785) 233 (E:193) F:0 L:0]

[Rate, wattage summery of DC2DCs, A:asic count, TMP: input output temperature]
[H:HW:2176Gh (0),W:999,L:0,A:15,MMtmp:0 TMP:(31)=>=>=>(0,76)]
[state of queues, not important]
Pushed 27 jobs , in HW queue 4 jobs (sw:2, hw:2)!
[statistics, wins:total shares, last minute shares, hw errors (wrong hash)]
min:49 wins:3350[this/last min:21/27] bist-fail:410, hw-err:1
[Leading zeroes, how much idle cycles over last secon/minute, computed rate, shares per board per minute]
leading-zeroes:42 idle promils[s/m]:0/0, rate:1887gh/s asic-count:1620 (wins:0+21)
Fan:80, conseq:200
AC2DC BAD: 0 0
[Running time / Idle time]
R/NR: 6376/0
RTF asics: 0
[Fet types (not important for you) and error counters (nothing to be afraid of, errors handled internally and do not effect rate)]
FET: 0:255 1:0
0 restarted 0 reset 0 reset2 0 fake_wins
0 stuck_bist 0 low_power 0 stuck_pll 0 runtime_dsble
0 purge_queue 0 read_timeouts 0 dc2dc_i2c 0 read_tmout2 0 read_crptn
0 purge_queue3 0 bad_idle
1 err_murata
Adapter queues: rsp=0, req=22

Could we have more detailed info?
Can we manipulate the freq limit for the asic chips?

What about some commands to configure Wifi with USB dongles?

thank you

1) This is as detailed as I can get without going here into logic of implementation.
2) Standard linux wifi control file in /etc/ and standard linux commands.