Are there power dissipation estimations for any of the ASIC products available ?
Not yet, I'm afraid to post simulation results as they may be wrong.AFAIK, our competitors didn't published their expectations too. But at least we know that it will be better than 45 nm FPGAs
Actually Bitfountain did publish their expectations:
Update
After further optimization and some trade-offs, we came up with this updated estimation results based on our improved design.
Hashrate: 1.00GH/s per chip
Area: 21.7mm^2 per chip
Power Consumption: 8.23W
Again remember that they are estimated from the RTL design and might have some differences to real products.
After further optimization and some trade-offs, we came up with this updated estimation results based on our improved design.
Hashrate: 1.00GH/s per chip
Area: 21.7mm^2 per chip
Power Consumption: 8.23W
Again remember that they are estimated from the RTL design and might have some differences to real products.