They've admitted to using a larger die size than their competitors.
Link? I haven't seen anything from them regarding die size, but I haven't been following too closely.
I'm also worried by their refusal to say how many chips are in the 60GH/s device. I count at least five people asking in this thread and still no answer.
Dude, he listed that information in the very first post of this thread: 110nm.
Chip Specification
Technology Summary:
TSMC 0.11- micron G process
He has previously posted that they would be using either 110nm or 130nm, but confirmed the details here.
Die size isn't the process node, it's how physically large the die is. IE, 5mmx5mm or 25mm^2, something like that.