Quote from: bitcoindaddy on November 07, 2012, 07:19:13 PM

Quote from: Keefe on November 07, 2012, 07:13:26 PM

Quote from: abeaulieu on November 07, 2012, 01:42:22 PM

Quote from: Keefe on November 07, 2012, 07:05:16 AM

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

It's not just the fabrication process size that matters. The implementation of the hardware is a huge factor.

Yep, so why do we only see the 2x "die shrink" advantage in these power estimates and nothing else? Where's the additional efficiency gain of going full custom? Shouldn't the BFL be 3x or 4x more efficient, not just 2x?

And I'm aware Inaba has already answered this by saying Tom's numbers are unrealistic. But I don't think either one has a working prototype, so we'll just have to wait and see.

Maybe they're "holding back" and will surprise us with better "real" numbers when the product ships.

Checkout this post from BFL which seems to support my position:
https://forums.butterflylabs.com/showwiki.php?title=FAQ:Bitforce+SC+ASIC+Product+Line

"While our numbers are very good, we are being conservative with our announce power figures and the likely power consumption will be even less."