Having personally worked on a project where our final product was an ASIC I can tell you that your chances of having a working first piece are almost zero.
You get everything working in Verilog on your FPGA development board and send the Verilog files to the fab. They do the layout, make the masks, produce the first lot, do testing, ship you the first parts. You get the parts and damn, guess what you forgot something dumb. So it's back to the fab with rev 2 of the Verilog files.
That's why the smart kids do hybrid structured ASICs with as many hard macros as possible for the first run. A couple grad students, a little money, some soldering parties, and you can have your personal mini-hashmonster in less than three months.
Obviously, this won't fly for a commercial production venture because you can only cram so much on taxi runs, but not even having this level of development is a bad sign for BFL.
Considering the market size it makes a lot more sense than going straight to a pure custom ASIC working directly with a foundry, i.e. $$$$$$.
Also I'm going to predict BFL eventually announces delays into January, their latest explanations + revised timeline appear irrationally optimistic.