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Re: Butterfly Labs November Update (ASIC Chips are "flawed". Delays.)
by
Bogart
on 28/11/2012, 18:57:12 UTC
Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.


Regards,
Nasser

You said the same thing yesterday on the BFL forums.  It doesn't make any more sense when you say it again here today.

If you haz chips that are not critically flawed, Y U no ship dem?

If they don't perform up to spec, that is indeed a flaw.  Yet you say there is no flaw?

Hearing things like this that don't make sense is making the flocks restless.