Quote from: Clearfly on November 28, 2012, 11:43:06 PM

Quote from: MinorMiner on November 28, 2012, 09:31:07 PM

Quote from: BFL-Engineer on November 28, 2012, 02:42:08 PM

Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.

Regards,
Nasser

Okay, so 'BFL-Josh' says 'There was a flaw in the chip that needed to be addressed' .. and now there isn't? Get on the same page, people.

Thats marketing speak and damage limitation.

I read it as voltage leakage (which is, as i understand it a risk on 65nm process). Either way it means chips are not in full production yet and issues are still being ironed out.

IOW, a respin.

How many iterations do you suppose there have been already? Do you suppose they were all high-volume "bullet runs", each with its own full-wafer mask set?

If it means a respin, the "week of the 11th" seems too soon, when it took 25+ days the last time.