Update
1. Our wafers are already in the slicing and packaging service. Whether we could beat everyone else in early delivering, or we have to revise and redo the wafers, will be known within the next two weeks.
An encouraging update! It means the chips at least passed the QC at the fab, and that slicing+packaging+testing is already under way. I'm hungry for more info, please return soon and fill in more blanks:
1) Recovered the ~5000 BTC from GLBSE yet? (I would like to just stop worrying about it...)
2) Did the fab really process 12 layers in 7 days, or was it simply information delay?? [Dec 05: "There are 12 layers left", Dec 12: "we are now in QC"]
3) What is the reason for deploying the second half of the chips later than the first? [Genuine question, I'm simply not smart enough that the reasons are obvious to me!]
I think I can say on behalf of all (at least many/most) stakeholders: Thanks, congrats, and keep up the great work!
With #3, from what friedcat has said in this thread, this is what seems to be going on: the chips are now out of the fab, are being packaged and tested, and soon as thats done they will be shipped to friedcat or another company to be inserted onto boards (he hasn't said whos manning the solder gun on this yet, or if he did, I missed it). He hasn't said whos manufacturing the boards (this should be easier to do than with FPGAs, btw) or if they're done yet or not.
The packaging, shipping to next location to be board mounted and have the assembled product QCed, and then being shipped to wherever friedcat has chosen to set these up for mining, can all be done concurrently depending on how the companies handle it.
Also, from what I understand, soon as mining has produced enough money for a second and possibly third run of ASICs, thats going to happen too.
I think that somewhat answers your question.