Ah, ok.  Thanks for the info.  I'll abandon that challenge for the time being then.  I think I will still try to get the Verilog working so I can run it at weekends

VHDL from scratch.  I write embedded software (ASM, C, C++) for a living, so the language syntax is easy enough.  The bit I'm struggling with at the moment is exactly what makomk has said - tailoring the HDL to the FPGA.  I still think in terms of high level code that has the correct behaviour in the simulator, not how best to utilise the available slices, flip flops, block rams etc.  With any luck this will come with time.  It seems that getting the VHDL working would be an interesting challenge when I start understanding things.