Quote from: Zeeks on January 28, 2013, 12:51:03 AM

This saga of ASICs is really troubling from an outsider perspective. I have no orders with anyone, waiting for them to start reaching miners before I decide if I want to start a mining farm.

There is Avalon who claims to have shipped yet has no tracking numbers. How is that even possible these days? All the carriers I use give you tracking info if you ask for it or not. Two weeks is also a bit too long for stuff to get out of China unless customs is holding it for an extra long time. Feels like they haven't actually shipped more than a couple units and are stalling for time, if they show no one any tracking info then they can use that as an excuse.

Then there is BFL who keeps pushing their dates back further and further with odd or cryptic issues. Some of their excuses don't make a lot of sense when you look at the other stuff they say which makes it seem like they are further behind than they are letting on.

And then there are the rest which seem to have all folded up.

It's very disconcerting but in the end I am so glad I waited to see how things turn out.

Lets do some basic math:
For existing FPGA design the best can be had is 23MHps/J. There is no reason to anticipate an improvement in FPGA power efficiency, yes, there can be marginal reduction of overhead and the FPGA can be scaled up, but it's efficiency will not increase all that much. Based on existing designs we can anticipate 25MH/J for FPGA. There is nothing special abut ASIC, most ASIC vendors just use a custom programmed FPGA; this is called FPGA to ASIC conversion. So at best ASIC will be 50MHps/J; and i am being VERY generous here. Also, designing a product based on FPGA is one thing, designing an FPGA is completely different. It would take millions of dollars to design a new FPGA.
For the boasted hash rates of 1+GHps we are still talking 25-50 W. This is not unreasonable, until you realize that USB cable provides 5V at 0.5A, which is 2.5W. So those FPGA/ASIC designs better show a mollex connector or something... With single USB you will not hash faster than 2.25/25=0.09GH.

Now lets do some more math:
I work as an electrical engineer and salaries range from $50K/y to $180K/y depending on experience and seniority. To get an FPGA/ASIC project of this scale done you will need 2 very good engineers forking full time for a year. So we talking $200K in salary minimum. You are probably talking closer to $300K in salary by the time you add in customer support, web dev etc. The manufacturers advertise "Limited supply" to not scare miners away. From hardware alone i dont think it is at all possible to make jalapenio for $160, but lets approach this issue from the other end. If they make 10,000 units, the company needs to get $30/unit just to cover bare minimum salaries. Which means all the hardware of something like Jalapeno must cost no more than $119. For this much the best FPGA they can get is like Cyclone III, which does not look cool enough to be beefy enough to do a GH/s. At 315MHz and at least 100 clock cycles per hash (by the time you sync all ins and outs you will waste more, i am being generous here) we are talking at 3.15 MHps per input path. Due to the number of available gates just under 200,000 i doubt you can do more than 10 (200,000/256/100=7. Cool

hashes in parallel. I am assuming 256 routes per hash since they are 256-bit hashes and 100 gates per hash. So with 3.15MHps*10 we have 31MHps. In Ideal perfect case, for an FPGA like Cyclone III we are talking (200,00/147,000=1.34) more HPS than from $200 spartan-6. With 100MHps on Spartan6 we would at best get 134MHps on something like Cyclone III, this 134MHps is a theoretical and unattainable number.

Conclusion: All of the FPGA promises are bs for the low prices listed. It is simply not possible to buy enough logic gates for this money to get the advertised MHps.
It would take millions of dollars to design a custom fpga and existing fpgas cost more than any of the advertised prices.