Quote from: Matthew N. Wright on February 05, 2013, 01:57:07 PM

If it were an ASIC, would it be just one chip?

Generally no and especially not for "first gen" product. The larger the die size the larger the % of chips lost due to fabrication errors. For a design like this you can't have a chip "half good" so any functional defect means a lost chip. The size of the die is likely based on the vendor (i.e. people actually making the chip) recommendation.

It is a tradeoff. A single 22GH/s chip would either need to be massively parallel (i.e. one chip is designed to split the work among multiple hashing engines working in parallel (multiple nonces checked per clock cycle) or it would need to run at an insanely high clock (to complete 22 GH/s using a single hashing engine would require a clock speed of 22 Ghz obviously impractical).

Based on the photo and specs my guess is that each Avalon chip completes a single SHA-256 double hash per clock and runs at ~275Mhz. So if you had a board with a single chip it would use about 2W and produce complete 275 million double SHA-256 hashes per second obviously that is impractical so a board consists of 80 chips working together to produce 22 GH/s (80 * 0.275 Gh/s per chip = 22 Gh/s per board). To do this with one chip at the same clock speed would require the chip have 80 hashing engines. That would make the die 80 times as large.

The entire unit is simply a controller, powersupply, and logic boards to route block headers to the individual hashing chips and "golden nonces" (diff 1 = 1 in 2^32 hashes) back to the controller for verification. How the work gets broken up is simply a design choice you could make a 66 GH/s miner using 66,000 chips with a hashrate of 1 Mh/s ea or a single chip with a hashrate of 66 GH/s. Everything being equal having fewer larger chips simplifies board design, assembly and production however larger chips mean higher power density (harder to cool 100W in one chip then 100W spread out over a board) and lower chip yields so neither extreme is attractive. The sweetspot tends to be in the middle.

The next gen (not batch2, or 3 but the next design) will get more parallel. Instead of 320 chips which have a single "hashing engine each" you could use 40 larger chips with 8 hashing engines. If ASIC production remains competitive maybe in a few generations you will see much larger chips capable of high GH/s speed (say 20 hashing engines inside a single chip running at 800 MHz completing 16 GH/s per chip).