Quote from: bardacuda on November 25, 2016, 08:25:23 PM

Quote from: Rusguy on November 25, 2016, 08:00:03 PM

Quote from: reb0rn21 on November 25, 2016, 07:50:44 PM

I don`t know how exact you can adjust memory access to GPU memory, but ppl that compare and cry here thet RX 4xx should be fast as 390x should first learn that any architecture is different, the driver is accessing GPU memory as best as it can, if zcash need many small accesses and if 256bit bus is not wide enough its logical that 384 or 512bit bus will be better, even when we know with 2xx and 39x GPU and memory clock is more "aligned" and in sync then on RX cards which usualu work 11xx/2000

CRYING here RX4xx is pointless if you know NOTHING about internel GPU arhitecture and even less about zcash prof of work algo and how its computed

Even if 480 and memory bandwidth 256bit bus still only used 50% of its capacity !!! And I think that the manufacturer knowingly went to such a move is likely for this new chip Polaris dostochno and bandwidth 256bit bus, with his new memory controller that provides a slightly lower performance than the 390 !!!
Sorry for my English

That would see the controller load from 390 models think it will give a small concept in this issue

R9 290 MC usage:

https://i.imgur.com/UX0NIVb.png

Quote from: nerdralph on November 18, 2016, 03:02:52 PM

Quote from: bensam1231 on November 18, 2016, 02:31:18 AM

Quote from: nerdralph on November 17, 2016, 08:09:59 PM

Quote from: bensam1231 on November 17, 2016, 04:26:18 PM

Do you also know if you want to check if a algo is memory limited, you can go into GPUZ and check out the MCU (memory controller unit) and see the load on it?

I think this is wrong. Although I primarily mine using Linux, I have a Windoze box that I use for testing cards. GPU-z appears to show only external bus bandwidth use (to the GDDR), and not the utilization of the bandwidth between the controller and core. In practical terms, a miner kernel may be using 200GB/s of memory bandwidth, but a significant percentage of it can be from the L2 cache. The collision counter tables in SA5 would be an example of this.

Do you have a source for this hypothesis? In all memory restricted algos that correlates to MCU usage. Pretty sure it pertains to any sort of memory overload, bandwidth or bus width...

My knowledge of the AMD GCN architecture (and computer architecture in general), and my experience writing OpenCL.

Loading controller slightly higher than the 480, but the GPU BPM temperature2 temperature is about the same as the GPU BPM temperature1, there is likely to interfere with the speed of the memory controller already that little bandwidth 256bit bus