Quote from: TransaDox on December 01, 2016, 01:33:43 AM

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True.
However, I see "ASIC resistance" used more as a blanket term for the phrase "Is it more cost effective to mine my coin using general hardware as opposed to making an 'Application Specific Integrated Circuit', whatever that 'circuit' may be" and its variants. That is, a purely economic term. Of course, if you subscribe to the supposition that a "specific circuit" will always be better than a "general circuit" for the specific case it is designed for.

Cost has nothing to do with it. The meaning is established. ASICS scale by parallelism. If an algorithm is atomic and memory light then ASICS are a good choice. They only have a fixed number of gates and creating memory out of those gates uses a lot of them.

As an example. The current hash calculation needs only the hash states and a simple counter for the on-chip memory which can then be applied to a non-changing memory of transactions-a constant, if you will. This can easily be scaled to multiple hash calculations in parallel on a single memory list of transactions.

If, instead of a counter, the hash was calculated on a varying number of transactions (1 then 2 then 3 and so on) then this is not the case. Scaling up the hash alone yields the same hash if the transaction list is constant and in order to calculate the hash for each (1,2,3...) transaction lists would require a huge amount of resources which the ASIC is unlikely to have. This method would be ASIC resistant.

I disagree, the decision to build specific hardware is a purely economic one - as it has been in all industries so far.
If a one percent increase in performance over generalized hardware is a cost effective move, specific hardware will be designed and built.