Quote from: laik2 on March 06, 2017, 11:08:20 AM

Quote from: quocthanh1302 on March 06, 2017, 09:22:37 AM

Quote from: dallase on January 29, 2017, 08:39:58 PM

Code:

MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
TRCDW 4:0 5bit Number of cycles from active to write
TRCDWA 9:5 5bit Number of cycles from active to write with auto-precharge
TRCDR 14:10 5bit Number of cycles from active to read
TRCDRA 19:15 5bit Number of cycles from active to read with auto-precharge
TRRD 23:20 4bit Number of cycles from active bank a to active bank b
TRC 30:24 7bit Number of cycles from active to active/auto refresh

#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa 5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf 5 bits

#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 4 bits

#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 7 bits

MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
TNOPW 1:0 2bit Extra cycle(s) between successive write bursts
TNOPR 3:2 2bit Extra cycle(s) between successive read bursts
TR2W 8:4 5bit Read to write turn
TCCDL 11:9 3bit Cycles between r/w from bank A to r/w bank B.
TR2R 15:12 4bit Read to read time
TW2R 20:16 5bit Write to read turn
---- 23:21 3bit Unused.
TCL 28:24 5bit CAS to data return latency

#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 # 5 bit

#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 # 3 bit

#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 # 4 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc

#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10

#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18

MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63

TRP_WRA 5:0 6bit From write with auto-precharge to active - 1.
---- 7:6 2bit Unused
TRP_RDA 13:8 6bit From read with auto-precharge to active - 1.
---- 16:14 3bit Unused
TRP 19:16 4bit Precharge command period - 1.
TRFC 26:20 7bit Auto-refresh command period - 1.
TCKE 31:28 4bit CKE power down exit timer.

#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf # 4 bit

#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 # 7 bit

# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING

can you show structure MISC2 in bits like RAS CAS MISC above, thanks.

THere is no TCKE in MC_SEQ_MISC_TIMING for GDDR5
I was doing it all wrong before I noticed that myself

Ya, that was from the old M56 register specs. I'll try and consolidate all I have here..

Code:

RAS
trcdw 4:0 5bit Number of cycles from active to write
trcdwa 9:5 5bit Number of cycles from active to write with auto-precharge
trcdr 14:10 5bit Number of cycles from active to read
trcdra 19:15 5bit Number of cycles from active to read with auto-precharge
trrd 23:20 4bit Number of cycles from active bank a to active bank b
trc 30:24 7bit Number of cycles from active to active/auto refresh
---- 31 1bit Unused?

CAS
tnopw 1:0 2bit Extra cycle(s) between successive write bursts
tnopr 3:2 2bit Extra cycle(s) between successive read bursts
tr2w 8:4 5bit Read to write turn
tccdl 11:9 3bit Cycles between r/w from bank A to r/w bank B.
tr2r 15:12 4bit Read to read time
tw2r 20:16 5bit Write to read turn
---- 23:21 3bit Unused?
tcl 28:24 5bit CAS to data return latency
---- 31:29 3bit Unused?

MISC
trpwra 5:0 6bit From write with auto-precharge to active - 1.
---- 7:6 2bit Unused?
trprda 13:8 6bit From read with auto-precharge to active - 1.
---- 15:14 2bit Unused?
trp 19:16 4bit Precharge command period - 1.
trfc 26:20 9bit Auto-refresh command period - 1.
---- 27 3bit Unused?

MISC2
pa2rdata 3:0 4bit
pa2wdata 7:4 4bit
faw 12:8 5bit 4 activate windows
tredc 15:13 3bit
twedc 20:16 5bit
t32aw 28:21 8bit 32 activate windows
twdatatr 31:29 3bit

PMG
tcksre 3:0 4bit
tcksrx 7:4 4bit
tcke_pulse 11:8 4bit
tcke 18:12 7bit
seq_idle 22:19 4bit
tcke_pulse_msb 23 1bit
seq_idle_ss 24 1bit

ARB
actrd 7:0 8bit
actwr 15:8 8bit
rasmactrd 23:16 8bit
rasmactwr 31:24 8bit

ARB2
ras2ras 7:0 8bit
rp 15:8 8bit
wrplusrp 23:16 8bit
bus_turn 31:24 8bit