A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device                          ; 5SGXEA7K2F40C2                            ;
; Logic utilization (in ALMs)     ; 32,617 / 234,720 ( 14 % )                 ;

In this device you should fit at least 6 miners, more if you can share resources and use the dsp blocks.

A 10ns clock gives a slack of  -1.9ns, which pretty bad performance. I don't understand why.

1) git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git

Before you start making a PCB you should get the tools to explore implementations and do simulations to make sure your implementation is working, also you would probably want to get a dev kit to play with before you design your own PCB. They come with schematics so you can see how things are done, even though that they are somewhat overengineered and have lots of stuff you don't need like serdes, pcie, ddr3 interfaces and so on.