Hi All. I am trying to implement the following on a Virtex 6. DCMs are no longer used on the Virtex 6 and have been replaced with MMCMs. So far I have swapped the DCM for an MMCM and am able to implement the design. But when I try to run the python script, it fails. I get a "Got bad message from FPGA: 240". I would appreciate any guidance you could provide. Thanks.
As you're probably not running at 120MHz you'll need to adjust the UART clock divider.
If you provide your clock frequency I can calculate the correct values for you.
Oh, and it would be interesting which Virtex 6 model this is, which frequency you can reach and how many LUTs/slices/FFs are used.
The device is the xc6vlx240t. I'm currently using the 200MHz clock on the device and have the MMCM set to 100MHz. The MMCM supports up to 800MHz.
Here's the utilization with a depth of 5.
Device utilization summary:
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Selected Device : 6vlx240tff1156-3
Slice Logic Utilization:
Number of Slice Registers: 50042 out of 301440 16%
Number of Slice LUTs: 86029 out of 150720 57%
Number used as Logic: 86028 out of 150720 57%
Number used as Memory: 1 out of 58400 0%
Number used as SRL: 1
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 86548
Number with an unused Flip Flop: 36506 out of 86548 42%
Number with an unused LUT: 519 out of 86548 0%
Number of fully used LUT-FF pairs: 49523 out of 86548 57%
Number of unique control sets: 12
IO Utilization:
Number of IOs: 3
Number of bonded IOBs: 3 out of 600 0%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 4 out of 32 12%
As you have lots of spare flipflops, you should probably cut the pipeline stages into halves by doubly-registering their output (xst will balance some logic into this additional clock cycle). You should manage to cross 200MHz that way.
The UART clock divider values for 100MHz are "01101100100" and "10100010110".