Post
Topic
Board Off-topic
Re: Butterfly Labs November Update (ASIC Chips are "flawed". Delays.)
by
MrTeal
on 24/04/2013, 17:17:18 UTC
Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.


Regards,
Nasser
Since I saw you were online today Nasser, can you comment on this quote by Josh in a Wired magazine article?
Quote
The problem was that Butterfly — based out of Kansas City, Missouri — banked on a cool design and a brand new chip manufacturing process and ended up getting in over its head. “We’ve hit quite a few snags along the way, says Butterfly Chief Operations Officer Josh Zerlan.

The company had to redo its initial chip designs, but the worst snag was in November, when the Butterfly got a hold of its first chip samples. They were basically too hot to work, Zerlan says. “The plastic packaging on the top of the chip just couldn’t exhaust the heat fast enough, so it basically melted the package.”
Link: http://www.wired.com/wiredenterprise/2013/04/bitcoin-mining-rigs/

Was Josh misquoted or incorrect, or did you get chip samples in that ran so hot they destroyed the QFN packages?