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Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
paszczakojad
on 25/04/2013, 05:10:48 UTC
Quote
When I replaced dsp_e with adder I got 302 MHz
I find it odd that your Fmax is dropping when you replace the DSPs with LUTs.  You may want to fiddle around with Vivado's settings to make sure register retiming (or whatever Vivado calls it) is enabled.  Alternatively, implement the adders as two stages of 16-bits each.  Since the DSPs that are being replaced are two stage (or three) anyway.

I used 2-stage adders, because DSP adders worked in 2 cycles and I didn't want to debug too much. IP core generator recommended 3 cycles for the best performance - I'll try that next.

After replacing dsp_e, dsp_wp and dsp_t1p I got 46% DSPs used - so it's enough to fit two cores.