I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.
I could easily increase it and I may still. My brief research indicated 1.5mm spacing as optimal. It may be worth spending $10 for test boards with 15,25,36 via pads and a bundle of 1/2W resistors placed around the pad body to simulate, before ordering final boards. Or with the prototype board use one bank of 16 and one of 25 to test difference.
If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1]. for the board ones you can do a circle of copper on the top layer (with no soldermask) as well
Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of
How are you doing the layer stackup? Which layer is the power/ground plane?
Definitely plan to add and the silkscreen now is just what Kicad did by default. I haven't looked at it yet for adding what I want and removing garbage like "PIN1".
I was working with a rather basic 1.6mm stack:
top 1.2V plane, 1oz
0.2 FR4
inner 1 3.3V plane, 0.5oz
1.2 FR4
inner 2 signal, 0.5oz
0.2 FR4
bottom GND plane, 1oz
But there is more GND planes under the switching supply, and a few signals escape on inner 1.
I'm open to suggestions but something unusual will push the board cost up. Part of keeping the cost down is that they batch with other boards, so go weird and it will likely push cost by 5-10x or more (for short runs anyway). I'd consider using a thin board to help heat pass to the back more easily and I can go 1.2mm total for the same cost. I'm just unsure of the downside to that.
What do you mean spend 10$ for test boards? The setup cost is usually several hundred dollars.
also, any reason you don't have an internal ground plane? I'm only familar with a 4 layer, 1 Vcc, 1 Gnd setup, where typically the signals are routed on the top and bottom only if at all possible, and the middle two layers are reserved for ground and power. The unused portions of the bottom layer can then be flooded with ground plane as well to facilitate heat transfer, especially around the QFN. the top layer can be flooded with the 1.2V plane or mini-planes
I think it may be very important to have internal ground plane that the QFN is directly connected to.